The present invention relates to a frequency measurement test circuit used to measure the frequency of a signal output from, e.g., a phase-locked loop incorporated in a large scale integrated circuit, and a semiconductor integrated circuit having the frequency measurement test circuit.
Conventionally, to test a large scale integrated circuit (to be referred to as an LSI hereinafter) incorporating a phase-locked loop (to be referred to as a PLL hereinafter), generally, the frequency in the locked state of the PLL is measured using an analog tester and digital tester, and it is checked whether the frequency has a desired value. That is, testing need be performed twice with the analog tester and digital tester. However, the analog tester and digital tester are expensive, and the measurement time is long because measurement must be performed twice. An apparatus capable of testing frequencies using only a digital tester has been disclosed.
FIGS. 3A and 3B show conventional test circuit. As shown in FIGS. 3A and 3B, conventional digital testers (test circuits) 11a and 11b are arranged outside digital integrated circuits (to be referred to as ICs hereinafter) 12 each incorporating a PLL. The digital testers 11a and 11b have external and internal frequency measurement devices 13a and 13b, respectively. The frequency measurement device 13a or 13b measures the frequency in the locked state of the PLL. The digital tester 11a or 11b determines whether the measured frequency has a desired value. Since such conventional digital tester 11a or 11b requires the frequency measurement device 13a or 13b, the circuit becomes complex. Japanese Patent Laid-Open No. 9-197024 has proposed a simple and inexpensive test circuit that solves the problem.
FIG. 4 shows the conventional test circuit disclosed in Japanese Patent Laid-Open No. 9-197024. The conventional test circuit disclosed in this prior art has two counters 22a and 22b which receive a signal output from a PLL 21. The two counters 22a and 22b are selected by a control signal CE whose duty ratio is 50%. The test circuit also has a comparator 23 for comparing the signal output from the counter 22a within a predetermined period with that output from the counter 22b within a predetermined period. The test circuit further has a decoder 24 for outputting a signal in association with the output signals from the counters 22a and 22b and comparator 23.
This conventional test circuit requires no frequency measurement device, and the circuit is simple. Since testing can be performed using only one tester, the circuit is less expensive than conventional circuits. However, the conventional test circuit disclosed in the above prior art requires the two counters 22a and 22b to detect that the phase is locked in the PLL 21. Hence, the measurement accuracy must be increased by prolonging the measurement time. However, to prolong the measurement time, the counters 22a and 22b must have a large circuit scale. In addition, since the duty ratio of the control signal CE for controlling the counters 22a and 22b must be 50%, very high accuracy is required. To solve these problems, a circuit for detecting the phase-locked state is generally provided in the PLL.
Recently, a demand has arisen for measurement of not only the frequency of the PLL but also the oscillation frequency of a voltage-controlled oscillator (to be referred to as a VCO hereinafter) incorporated in the IC. The above-described circuit that receives the lock detection signal from the PLL can measure only the frequency in the phase-locked state of the PLL.